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TOPLEVEL ?= top_mmu
TOPLEVEL_LANG ?= verilog

PWD=$(shell pwd)
COCOTB ?= $(PWD)/../../cocotb

ifeq ($(OS),Msys)
WPWD=$(shell sh -c 'pwd -W')
PYTHONPATH := $(WPWD)/../model;$(PYTHONPATH)
else
WPWD=$(shell pwd)
PYTHONPATH := $(WPWD)/../model:$(PYTHONPATH)
endif
export PYTHONPATH

VERILOG_SOURCES = $(WPWD)/../hdl/ram_sp_sr_sw.v
VERILOG_SOURCES += $(WPWD)/../hdl/tscale.v
VERILOG_SOURCES += $(WPWD)/../hdl/fifo.v
VERILOG_SOURCES += $(WPWD)/../hdl/axi_data_channel.v
VERILOG_SOURCES += $(WPWD)/../hdl/mmu.v
VERILOG_SOURCES += $(WPWD)/top_mmu.v
INCLUDE_PATH =  $(WPWD)/../hdl
COMPILE_ARGS = -I $(INCLUDE_PATH)
GPI_IMPL := vpi

export TOPLEVEL_LANG

MODULE ?= test_mmu

include $(COCOTB)/makefiles/Makefile.inc
include $(COCOTB)/makefiles/Makefile.sim

MAKEFILE_LIST = Makefile
help:           		## Show this help.
	@echo ": (No target) 			 Compile Verilog, Python sources code and run simulation"
	@echo "clean: 				 Remove intermediate simulation files"
	@fgrep -h "##" $(MAKEFILE_LIST) | fgrep -v fgrep | sed -e 's/\\$$//' | sed -e 's/##//' | grep -v '#####'

.PHONY: covered
covered: mmu.cov mmu.dcov 	## Generate 2 coverage reports (mmu.cov: summary one and mmu.dcov: detailed one) 

mmu.cov: mmu.cdd
	covered report -d s -o mmu.cov -s mmu.cdd

mmu.dcov: mmu.cdd
	covered report -d d -o mmu.dcov -s mmu.cdd

mmu.cdd: dump.vcd
	covered score -t MMU -i top_mmu.dut_mmu -v ../hdl/mmu.v -I ../hdl -y ../hdl -rW -e ram_sp_sr_sw -ep -o mmu.cdd -vcd dump.vcd

.PHONY: clean_more
clean_more: 			## Remove dump.vcd and intermediate corerage file mmu.cdd
	-rm -f dump.vcd mmu.cdd ../hdl/a.out