You can download here and test with your own files the audio compression effect of this algorithm. The complexity is limited to one addition and two 16 bits multiplications per samples. The divisions are computed with pre-computed tables, to make it efficient for implementations on tiny processors like Cortex-M0. In the example provided, the gain is set for up to 35dB, the other parameters are preset for this demo (attack and decay control, energy limitation to comply with national regulations, compression level at each input level like in the diagram below).
This program implements an adjustable interpolator used for the sampling rate conversion (SRC). The code is ported to Cortex-M4 / M7 and Cortex-A with or without NEON. The documentation is here
Several configurations are precomputed and can be prepared depending on the memory size constraints of your device. The bit-exact demonstration files and executable (BATCH_SRC.BAT) are located here.
This program implements an interpolator used for the compensation of frequency drifts. The technique is based on a first-order recursive filter. There is one input parameter to set the amount of drift to be compensated for. The amount of drift is usually in the range of few percent down to few ppm.
The code is written in fixed-point C using Q15 and Q31 arithmetics. When ported on CortexM4 the code is processing one sample every 20 cycles (1 MHz CPU load for a stream at 48kHz). This number is obtained without the need to optimize the critical loops in assembly language.
The technical documentation is located here.
The demonstration files and executable (BATCH_DRIFT.BAT) are located here
This program implements the decimation of a Pulse Density bit-stream. The typical use-case of this program is to decimate the PDM stream of a microphone to the usual audio sampling-rates. For example 16kHz for the keyword recognizer of Alexa voice services.
A bit-exact demonstration files and executable (BATCH_SRC.BAT) is located Here.
The code is ported and benchmarked for ARM Cortex-M4 / M7, and can be executed on any processor using 32-bits arithmetic. The first processing stage is a 4th order CIC decimator with decimation rate of 32 or 64, followed by an half-band decimator and DC-offset canceller using floating point arithmetic.
Example with a PDM rate is 2.048MHz with an Over Sampling Ratio (OSR) of 128, the targeted sampling rate is 2.048MHz/128 = 16kHz. The CIC decimator consumes 9.5 cycles/bits of a Cortex-M7, 39 cycles/samples at OSR=2 for the second decimator, 10 cycles for the DC-offset canceller.