System MMU provides 2 main functions :
Virtual to physical address translation
Memory protection
System MMU upstream port is directly connected to 1 master or connected to multiple masters via an interconnect.
Non-CPU master see contiguous memory space and remove the need to allocate fixed physical memory space or to manage memory fragmentation via a scatter-gather DMA.
HDL: Verilog.
Verification Language: Python
CAD Tools (Open tools): 
Simulation tool: Icarus Verilog (http://iverilog.icarus.com/)
TestBench environment: Cocotb (http://cocotb.readthedocs.io/en/latest/index.html)
Code Coverage tool: Covered (http://covered.sourceforge.net/)
Synthesis suite: Yosys (http://www.clifford.at/yosys/documentation.html)