;@/* ------------------------------------------------------------------------- */
;@/* Copyright (c) 2016 FIRMWARE DEVELOPMENTS SAS                              */
;@/* ------------------------------------------------------------------------- */
;@/* This program is free software: you can redistribute it and/or modify      */
;@/* it under the terms of the GNU Lesser Public License as published by       */
;@/* the Free Software Foundation, version 3 of the License.                   */
;@/*                                                                           */
;@/* This program is distributed in the hope that it will be useful,           */
;@/* but WITHOUT ANY WARRANTY; without even the implied warranty of            */
;@/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             */
;@/* GNU Lesser Public License for more details.                               */
;@/*                                                                           */
;@/* You should have received a copy of the GNU Lesser Public License          */
;@/* along with this program.  If not, see <http://www.gnu.org/licenses/>.     */
;@/* ------------------------------------------------------------------------- */
;@/* Purpose     : Biquads for Cortex-M4/M7                                    */
;@/* File:       : arm_biquad_cascade_df1_fast_q15_fwd_asm.s                   */
;@/* Author      : Laurent Le Faucheur                                         */
;@/* Created     : May 2016                                                    */
;@/* Description : One subroutine computing one biquad                         */
;@/* Release     : 1.0                                                         */
;@/* ------------------------------------------------------------------------- */ 
;@  .syntax unified
;@  .cpu      cortex-m4
;@  .text
;@  .global arm_biquad_cascade_df1_fast_q15_fwd_asm
    EXPORT arm_biquad_cascade_df1_fast_q15_fwd_asm
    AREA     ||.text||, CODE, READONLY, ALIGN=2
;@ 
;@ GNU SYNTAX       // no END  and  :
;@  .syntax unified
;@  .cpu cortex-m4
;@  .text
;@  .global arm_biquad_cascade_df1_fast_q15_fwd_asm    
    
;@ arm_biquad_cascade_df1_fast_q15_fwd_asm  (
;@ int r0   state of the direct path [zm1 zm2]
;@ int *r1  pointer to the state of the recursive path [ym1 ym2]
;@ int *r2  pointer to input samples
;@ int *r3  pointer to output samples
;@ int r4   FIR coefficients [0  b0]
;@ int r5   FIR coefficients [b2 b1]
;@ int r6   IIR coefficients [a2 a1]
;@ int r7   scaling - must be below or equal to 0
;@ int r8   block size
;@ )
;@
;@ REGISTER USAGE :
;@ int r0   state of the direct path [zm1 zm2]
;@ int r1   state of the recursive path [ym1 ym2]
;@ int r2   pointer to input samples
;@ int r3   pointer to output samples
;@ int r4   FIR coefficients [b1 b0]
;@ int r5   FIR coefficients [b2 b1]
;@ int r6   IIR coefficients [a2 a1]
;@ int r7   scaling
;@ int r8   block size
;@ int r9   acc1
;@ int r10  input data
;@ int r11  acc2
;@ int r12  *state_iir
;@ 
arm_biquad_cascade_df1_fast_q15_fwd_asm

;@ CODE SOURCE COMES FROM DECIPHERING OF src_biq_m4.otp
;@ CONTACT http://firmware-developments.com/

;@-----------------------------------------------------------------------------
    END

