REM ========================================================
REM DRIFT COMPENSATION TEST BENCH
REM CHECKS SEVERAL DRIFT VALUES ON THE SAME FILE
REM ========================================================

ECHO ON

REM ========================================================
REM ARITHMETICS 16x16 WITH 32BITS ACCUMULATOR
REM LOW-COMPLEXITY ALGORITHM, BENCHMARKED AT 18 CYCLES PER
REM SAMPLE ON A CORTEXM4 AT 12MHZ, 0 WAIT-STATES
REM THE CODE WAS COMPILED USING GCC -O3, WITHOUT ASSEMBLY
REM OPTIMIZATIONS.
REM INPUT FILE IS 24BITS AND RESCALED TO 16BITS ON FSCANF
REM ========================================================

REM TEST WITH +1% FREQUENCY ERROR COMPENSATION
FRCDLY   0.01
COPY TEST24_ASRC.TXT TEST24_OUTPUT_10000PPM.TXT

REM TEST OF +1000PPM FREQUENCY ERROR COMPENSATION
FRCDLY  0.001
COPY TEST24_ASRC.TXT TEST24_OUTPUT_1000PPM.TXT

REM TEST OF +100PPM FREQUENCY ERROR COMPENSATION
FRCDLY 0.0001
COPY TEST24_ASRC.TXT TEST24_OUTPUT_100PPM.TXT

REM TEST WITH -1% FREQUENCY ERROR COMPENSATION
FRCDLY  -0.01
COPY TEST24_ASRC.TXT TEST24_OUTPUT_M10000PPM.TXT

REM TEST OF -1000PPM FREQUENCY ERROR COMPENSATION
FRCDLY -0.001
COPY TEST24_ASRC.TXT TEST24_OUTPUT_M1000PPM.TXT

REM TEST OF +100PPM FREQUENCY ERROR COMPENSATION
FRCDLY -0.0001
COPY TEST24_ASRC.TXT TEST24_OUTPUT_M100PPM.TXT
DEL TEST24_ASRC.TXT

REM PAUSE